The present invention relates to FIR (Finite Impulse Response) filters and ramp-up/-down control circuits using the same and, more particularly, to FIR filters for controlling the transmission power level of a transmission circuit in a radio transmitter/receiver and ramp-up/-down control circuits using the same.
In the usual transmitter for performing CDMA (Code Division Multiple Access) transmission, transmission data is subjected to a digital signal processing circuit to a digital signal process, and then subjected to frame signal processing. The resultant transmission data is subjected to spreading process. Thus obtained transmission data is filtered in an FIR filter for bandwidth limitation. In the FIR filter FIR coefficient or data zero is produced on the basis of a control signal produced from a ramp-up/-down signal which is synchronized to the transmission data and represents the time section of data to be transmitted.
FIG. 10 is a block diagram showing the general construction of the transmitter for the CDMA transmission. As shown in the Figure, a transmitter for CDMA transmission comprises a digital part 121, an analog part 122 and an antenna 123. The digital part 121 includes a digital signal processing circuit 12a for performing digital signal processing (including a spreading process) on transmission data, an FIR filter 12b for bandwidth limiting and a D/A converter 12c for converting digital data to analog signal. The analog part 122 has an LPF (filter) 12d, a modulator 12c, an IF amplifier 12f, a mixer 12g and an RF amplifier 12h. 
As is well known in the art, in the transmitting for radio communication, at the start and end of transmission or at the time of burst transmission in time division transmission (including the case of packet transmission), the spectrum of the transmission signal is spread to have adverse effects on the transmitting operation. This is so because when transmission data rises sharply, the spectrum of the transmission signal is greatly spread at the rise time, thus causing frequency-wise interference with other channels. A similar problem arises even at the fall time of the transmission signal. Accordingly, it is prescribed as standard that a ramp-up and a ramp-down time sections are to be normally provided before and after effective transmission data.
Japanese Patent Laid-Open No. 8-46485 discloses a prior art means for solving the above problems. As shown in FIG. 11, the means comprises an n-bit shift register 301 constituted by n bit registers D1 to Dn, a memory 302 and a D/A converter 303. A signal of n bits outputted from the shift register 301 and a burst timing signal which is one-bit signal, constitute a sum bit (i.e., (n+1)-bit) signal, which serves as address signal for the memory 302. The memory 302 is of such a memory capacity which is called by (n+1) bits. The D/A converter 303 converts digital data outputted from the memory 302 to analog signal. An FIR filter can be realized by the above construction.
The FIR filter shown in FIG. 11 performs an operation of reading out a filter output with a ramp-up and a ramp-down parts from the memory 302 under control of the burst timing signal. Therefore, when the tap number (i.e., number of shift register stages) is increased, the memory capacity of the employed memory should also be increased, and therefore the circuit scale is increased.
It is conceivable to effect the ramp-up and -down by controlling GCA (gain control amplifier) analog-wise in such a manner as providing level changes with provision of an output multiplier or providing a separate ramp-up/-down waveform generating circuit and adding a ramp-up/-down signal generated therein to the transmission signal. Even such a method, however, has drawbacks that the power consumption and the circuit scales are increased, and cannot solve the above problems inherent in the prior art.